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[ AK7735A ] 018002104 - e - 00 - pb 201 8/03 - 1 - 1. g eneral d escription the ak 7735a is a highly integrated digital signal processor, including a 24 - bit stereo adc with mic gain amplifiers, a 24 - bit stereo adc with input selector, two 32 - bit stereo dacs, 2 stereo sampling rate convertors supporting the sampling frequency up to 192khz and dual dsps for aud io process. each dsp has 3072 step/fs (when fs=48khz) parallel processing power. as the ak 7735a is a ram based dsp, it is freely programmable for user requirements of acoustic effects. the ak 7735a is available in a 48 - pin lqfp package. 2. f eatures dual dsp: ( dsp1 and dsp2 have the same specification. memory a reas are shared by them ) - word length : 28 - bit ( simple floating point supported ) - instruction cycle : max . 6.8 ns ( 3072 fs at fs=48khz) - multiplier : 24 x 24 48 - bit ( double precision arithmetic available ) - divider : 24 / 24 24 - bit ( floating point normalization function ) - alu: 52 - bit arithmetic operation (with 4bits overflow margin ) - program ram : 4096 - word x 36 - bit - coefficient ram : 6144 - word x 24 - bit - data ram : 4096 - word x 28 - bit - delay ram : 12288 - word x 28 - bit - jx pins (interrupt) - independent power management function for dsp1, dsp2 adc1: 24 - bit stereo adc with mic gain amplifiers - sampling frequency : fs = 8khz ~ 192khz - channel independent analog gain amplifiers (0~18db(2db step), 18~36db(3db s tep)) - differential input or single - ended input - adc characteristics s/n: 10 6 db (fs=48khz , differential input, mic gain=0db ) - channel independent digital volume control (24db adc2: 24 - bit stereo adc with input selector - sampling frequency : fs = 8khz ~ 192khz - analog input selector : differential in put x1 or single - ended input x2 or pseudo - differential input x 1 - adc characteristics s/n: 10 6 db (fs=48khz , differential input ) - channel independent digital volume (24db ~ - 103db, 0.5db step, mute) - digital hpf for dc offset cancelling - 4 types of digital filter for sound color selection ak 7735a dual dsp with 4chadc + 4chdac + 4chsrc
[ AK7735A ] 018002104 - e - 00 - pb 201 8/03 - 2 - dac: advanced 32bit dac - 2ch x 2 - sampling frequency : fs = 8khz ~ 192khz - single - ended output - dac characteristics s/n: 108db (fs=48khz) - channel independent digital volume control (12db ~ - 115db, 0.5db step, mute) - 4 types of digital filter for sound color selection src: - 2ch x 2 - fsi = 8khz ~ 192khz, fso = 8khz ~ 192khz (fso/fsi = 0.167 ~ 6.0) digital interfaces - digital input port x 4 ( m ax 32ch , in tdm mode ) - digital output port x 4 ( m ax 32ch , in tdm mode ) - independent lrck/bick port x 3 - data format : msb 32, 24bit / lsb 2 4, 20, 16bit / i 2 s - pcm short / long frame supported - tdm format supported (max : 8ch / 256fs, fs=96khz) pll circuit p interface : spi( max 6 mh z ) / i 2 c( 400khz fast mode, 1mhz fast mode p lus) power supply : analog: avdd: 3.0v ~ 3.6v ( typ . 3.3v) digital: lvdd: 3.0v ~ 3.6v ( typ . 3.3v) (3.3v 1.2v regulator integrated ) i/f vdd33: 3.0v ~ 3.6v ( typ . 3.3v) tvdd: 1.7v ~ 3.6 v ( typ . 3.3v) operating temperature range : ta = - 40 ~ 85 ? package : 48 - pin lqfp (7mm x 7mm, 0.5mm pitch)
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 3 - 3. table of contents 1. general description ................................ ................................ ................................ .......................... 1 2. features ................................ ................................ ................................ ................................ ............ 1 3. table of contents ................................ ................................ ................................ .............................. 3 4. block diagrams ................................ ................................ ................................ ................................ . 4 block diagram ................................ ................................ ................................ ................................ ... 4 dsp block diagram ................................ ................................ ................................ ........................... 5 5. pin con figurations and functions ................................ ................................ ................................ ..... 6 pin configurations ................................ ................................ ................................ ............................. 6 pin functions ................................ ................................ ................................ ................................ ..... 7 handling of unused pins ................................ ................................ ................................ ................. 10 internal pulled - down pins status ................................ ................................ ................................ .... 10 power - down status of output pins ................................ ................................ ................................ .. 11 6. absolute maximum ratings ................................ ................................ ................................ ............ 12 7. recommended operating conditions ................................ ................................ ............................ 12 8. electrical characteristics ................................ ................................ ................................ ................. 13 analog characteristics ................................ ................................ ................................ .................... 13 power consumption ................................ ................................ ................................ ........................ 18 9. d igital filter characteristics ................................ ................................ ................................ ............ 19 adc block ................................ ................................ ................................ ................................ ....... 19 dac block ................................ ................................ ................................ ................................ ....... 23 src block ................................ ................................ ................................ ................................ ....... 27 10. dc characteristics ................................ ................................ ................................ .......................... 29 11. switching characateristics ................................ ................................ ................................ .............. 30 system clock ................................ ................................ ................................ ................................ .. 30 power down ................................ ................................ ................................ ................................ .... 30 serial data interface (sdin1 ~ sdin4, sdout1 ~ sdout4) ................................ ....................... 31 spi interface ................................ ................................ ................................ ................................ .... 34 i 2 c interface ................................ ................................ ................................ ................................ ..... 36 12. recommended external circuits ................................ ................................ ................................ .... 37 connection diagram ................................ ................................ ................................ ....................... 37 periph eral circuit ................................ ................................ ................................ ............................. 39 13. package ................................ ................................ ................................ ................................ .......... 41 outline dimensions ................................ ................................ ................................ ......................... 41 materi al and lead finish ................................ ................................ ................................ ................. 41 marking ................................ ................................ ................................ ................................ ............ 42 important notice ................................ ................................ ................................ .......................... 43
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 4 - 4. block diagram s block diagram figure 1 . block diagram
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 5 - dsp block diagram figure 2 . dsp block diagram note * 1 . coefficient ram, data ram, delay ram, program ram areas are shared by dsp1 and dsp2 and the sizes are configurable by control registers. tmp 8 28bit sdout3 cp0, cp1 dp0, dp1 d ata ram 4096 w x 2 8 bit max mpx 2 4 mpx2 4 x y multiply 2 4 2 4 48 bit micon i/f control program ram 4096 w 36 bit max dec pc s tack : 8 l evel (max) mul dbus shift a b alu 52 bit o verflow margin: 4 bit dr0 ? 3 over flow data generator division 24 ? 24 2 4 peak detector se rial i/f cbus ( 2 4 bit) dbus(2 8 bit) 4 8 bit 28 bit 48 bit 52 bit 52 bit 12288 w x 2 8 bit max p tmp (lifo) 6 2 8 bit d l p0, d l p1 52 - bit tmp 12 28 bit ofr eg 64 w x 1 4 bit d e lay ram coefficient ram 6144 2 4 bit max pointer 2048w unit 2048w unit 4096w unit 2048w unit 2 8bit x fifo16 dtmp ( connection between dsp 1/2 ) 2 x 24 bit din4 2 x 24 bit din3 2 x 24 bit din2 2 x 24 bit din1 2 x 32bit dout4 2 x 32bit dout3 2 x 32bit dout2 2 x 32bit dout1 2 x 24 bit din 6 2 x 24 bit din 5 2 x 32bit dout 6 2 x 32bit dout 5
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 6 - 5. pin configurations and functions pin configurations inn2 ain2lp/ain3l ain2ln/ain4l ain2rp/ain3r ain2rn/ain4r lvdd dvss3 avdrv pdn si/i2cfil sclk/scl so/sda - - 36 35 34 33 32 31 30 29 28 27 26 25 ain1r/inp2 37 24 csn inn1 38 lvdd 23 sto/rdy/sdout2 ain1l/inp1 39 22 - dvss2 mpref 40 tvdd 21 - tvdd mpwr 41 20 sdout1/rdy avdd - 42 avdd 19 bick1 avss - 43 18 lrck1 vcom 44 17 sdin1 vrefh 45 16 bick2/jx2 vrefl 46 15 lrck2/jx1 aout1r 47 vdd33 14 sdin2/jx0 aout1l 48 13 xto 1 2 3 4 5 6 7 8 9 10 11 12 - - aout2r aout2l testi lrck3 sdout4/gpo2 bick3 sdout3/clko/gpo1 sdin3/jx3 sdin4 dvss1 vdd33 xti AK7735A top view input output in/out - power
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 7 - pin functions no. pin name i/o function supply power 1 aout2r o dac2 rch analog output pin this pin outputs hi z during hi z during
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 8 - no. pin name i/o function supply power 23 sto o status output pin this pin outputs pin 2 c mode i 2 c i/f chip address pin this pin must be pulled up or pulled down. 25 so o serial data output pin for spi i/f this pin outputs 2 c i/f this pin outputs 2 c i/f 27 si i serial data input pin for spi i/f tvdd i2cfil i i 2 c i/f mode select input pin i2cfil = l: fast mode (400khz) = h: fast mode plus (1mhz) ( pdn pin should be held l when power is supplied.
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 9 - no. pin name i/o function supply power 32 ain2rn i adc2 rch inverted differential input 2 pin adc2 rch pseudo - differential ground input pin avdd ain4r i adc2 rch single - ended input 4 pin 33 ain2rp i adc2 rch non - inverted differential input 2 pin adc2 rch pseudo - differential signal input pin avdd ain3r i adc2 rch single - ended input 3 pin 34 ain2ln i adc2 lch inverted differential input 2 pin adc2 lch pseudo - differential ground input pin avdd ain4l i adc2 lch single - ended input 4 pin 35 ain2lp i adc2 lch non - inverted differential input 2 pin adc2 lch pseudo - differential signal input pin avdd ain3l i adc2 lch single - ended input 3 pin 36 inn2 i adc1 rch inverted differential input 2 pin avdd 37 ain1r i adc1 rch single - ended input 1 pin avdd inp2 i adc1 rch non - inverted differential input 2 pin 38 inn1 i adc1 lch inverted differential input 1 pin avdd 39 ain1l i adc1 lch single - ended input 1 pin avdd inp1 i adc1 lch non - inverted differential input 1 pin 40 mpref o ripple filter pin for microphone power supply connect a 1 f ceramic capacitor between this pin and avss. do not connect this pin to an external circuit. avdd 41 mpwr o power supply output pin for microphone this pin outputs hi z durin durin hi z durin hi z durin
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 10 - handling of unused pins unused i/o pins must be connected appropriately. classification pin name setting analog mpref, mpwr, ain1l/inp1, inn1, ain1r/inp2, inn2, ain2lp/ain3l, ain2ln/ain4l, ain2rp/ain3r, ain2rn/ain4r, aout1l, aout1r, aout2l, aout2r open digital xti, xto, sdout1/rdy, sto/rdy/sdout2, sdout3/clko/gpo1, sdout4/gpo2 open sdin4, sdin3/jx3, sdin2/jx0, sdin1, lrck1, bick1, lrck2/jx1, bick2/jx2, lrck3, bick3 , testi connect to dvss1 / dvss2 table 1 . handling of unused pins i nternal pulled - down pin s status no. pin name power down status pdn pin = l h pdn pin = h k k k k (46 k) k (46 k) k (46 k) k (46 k) k (46 k) k (46 k) k k k k
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 11 - power - down status of output pins no pin name i/o power - down s tatus no pin name i/o power - down status 44 vcom o l l hi z hi z hi z l hi z l hi z l hi z l hi z l
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 12 - 6. absolute maximum ratings (avss=dvss1=dvss2=dvss3=0v * 3 ) parameter symbol min. max. unit power supplies analog digital1(core) digital2(i/f) digital3(i/f) difference (avss, dvss1, dvss2, dvss3) * 3 avdd lvdd tvdd vdd33 gnd ? ? 7. recommended operating conditions (avss=dvss1=dvss2=dvss3=0v * 3 ) parameter symbol min. typ. max. unit power supplies analog digital1(core) digital2(i/f) digital3(i/f) difference1 difference2 difference3 difference4 avdd lvdd tvdd vdd33 avdd C C C C be held l when power is supplied. the pdn pin is allowed to be h after all power supplies are applied and settled. * 8 . do not turn off the power supply of the ak 7735a with the power supply of the peripheral devic e turned on. when using the i 2 c interface, pull - up resistors of sda and scl pins should be connected to tvdd or less voltage. warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet.
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 13 - 8. electrical characteristics analog characteristics 1. mic amp (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v ; adc1vl/r bit s =0) mic amp parameter min. typ. max. unit input impedance 14 20 26 k 2. mic bias output (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v ; measurement frequency =20hz~20khz) mic bias parameter min. typ. max. unit output voltage * 9 2.3 2.5 2.7 v load resistance 2 - - k
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 14 - 3. mic amp + adc1 (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v; signal frequency =1khz; 24bit data; bick=64fs; @ fs=48khz , measuremen t frequency bw=20hz ~ 20khz; @ fs=96khz ,192khz , bw=20hz ~ 40khz; adc1vl/r bit s =0; mgnl/r[3:0] bits= 0x0 (0db) ; differential input, unless otherwise specified. ) notes * 10 . inp1, inn1, inp2 and inn2 pins . when using differential input mode, it is prohibited to input signal to only one side like pseudo differential input. * 11 . ain1l and ain1r pins . * 12 . inter - channel isolation with - 1dbfs signal input. * 13 . adc1vl/r bit s = 0, mgnl/r[3:0] bits = 0x0 (0db). input full - scale voltage is proportional to avdd (0.7 x avdd). * 14 . adc1vl/r bit s = 0, mgnl/r[3:0] bits = 0x9 (+18db). input full - scale voltage is proportional to avdd (0.088 x avdd). * 15 . adc1vl/r bit s = 1, mgnl/r[3:0] bits = 0x0 (0db). in put full - scale voltage is proportional to avdd (0. 86 x avdd). * 16 . common mode rejection ratio when inputting 1khz, 100mvpp sine wave to both differential inputs. the value refers to the case when input ting a 1khz , 100mvpp sine wave as differential input. mic amp + adc1 parameter min. typ. max. unit resolution - - 24 b it input full scale voltage * 10 differential input * 13 2.1 2.3 2.5 vpp differential input * 14 0.264 0.290 0.315 differential input * 15 2.55 2.83 3.11 input full scale voltage * 11 single - ended input * 13 2.1 2.3 2.5 vpp single - ended input * 14 0.264 0.290 0.315 single - ended input * 15 2.55 2.83 3.11 s/(n+d) ( - 1dbfs) fs=48khz * 13 85 95 - db fs=48khz * 14 - 87 - fs=96khz * 13 - 92 - fs=96khz * 14 - 84 - fs=192khz * 13 - 92 - fs=192khz * 14 - 84 - dynamic range ( - 60dbfs) fs=48khz (a - weighted) * 13 98 106 - db fs=48khz (a - weighted) * 14 - 95 - fs=96khz * 13 - 99 - fs=96khz * 14 - 89 - fs=192khz * 13 - 99 - fs=192khz * 14 - 89 - s/n fs=48khz (a - weighted) * 13 98 106 - db fs=48khz (a - weighted) * 14 - 95 - fs=96khz * 13 - 99 - fs=96khz * 14 - 89 - fs=192khz * 13 - 99 - fs=192khz * 14 - 89 - inter - channel isolation * 12 90 105 - db channel gain mismatch - 0.0 0.3 db cmrr * 16 60 80 - db
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 15 - 4. adc2 (ta=25 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v; signal frequency =1khz; 24bit data; bick=64fs; @ fs=48khz, measurement frequency bw=20hz ~ 20khz; @ fs=96khz,192khz, bw=20hz ~ 40khz; adc2vl/r bits=0; differential input , unless otherwise specified. ) notes * 17 . ain2lp, ain2ln, ain2rp and ain2rn pins . * 18 . ain3l, ain3r, ain4l , ain4r pins and ain2lp , ain2 r p pins when ad2psde bit = 1 . * 19 . adc2vl/r bit s = 0 . input full - scale voltage is propotional to avdd (0.7 x avdd). * 20 . adc2vl/r bit s = 1 . input full - scale voltage is propotional to avdd (0. 86 x avdd). * 21 . common mode rejection ratio when inputting1khz, 100mvpp sine wave to both pseudo - differential signal input and ground inputs. the value refers to the case wh en inputting a 1khz, 100mvpp sine wave as pse udo - differential input. adc2 parameter min. typ. max. unit resolution - - 24 bit input impedance 14 20 26 k * 19 pseudo - differential input 2.1 2.3 2.5 vpp single - ended input * 20 pseudo - differential input 2.55 2.83 3.11 s/(n+d) ( - 1dbfs) fs=48khz 85 95 - db fs=96khz - 92 - fs=192khz - 92 - dynamic range ( - 60dbfs) fs=48khz (a - weighted) 98 106 - db fs=96khz - 99 - fs=192khz - 99 - s/n fs=48khz (a - weighted) 98 106 - db fs=96khz - 99 - fs=192khz - 99 - inter - channel isolation * 12 90 105 - db channel gain mismatch - 0.0 0.3 db cmrr (differential input) * 16 60 80 - db cmrr (pseudo - differential input) * 21 55 75 - db
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 16 - 5. dac (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v; signal frequency =1khz; 32bit data; bick=64fs; @ fs=48khz , measurement frequency bw=20hz ~ 20khz; @ fs=96khz,192khz , measurement frequency bw=20hz ~ 40khz) dac1 dac2 parameter min. typ. max. unit resolution - - 32 bit output voltage * 22 2.55 2.83 3.11 vpp s/(n+d) (0dbfs) fs=48khz 80 91 - db fs=96khz - 89 - fs=192khz - 89 - dynamic range ( - 60dbfs) fs=48khz (a - weighted) 100 108 - db fs=96khz - 101 - fs=192khz - 101 - s/n fs=48khz (a - weighted) 100 108 - db fs=96khz - 101 - fs=192khz - 101 - inter - channel isolation (fin=1khz) * 23 90 110 - db channel gain mismatch - 0.0 0.7 db load resistance * 24 10 - - k
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 17 - 6. src (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v; signal frequency =1khz; 24bit data; measurement frequency bw=20hz ~ fso/2) src parameter symbol min. typ. max. unit resolution - - 24 bit input sample rate fsi 8 - 192 khz output sample rate fso 8 - 192 khz thd+n (input=1khz, 0dbfs) audio mode (srcfaud bit = 1, srcfec bit 0) 0, srcfec bit 0) 1, srcfec bit 0) 0, srcfec bit 0)
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 18 - power consumption (t a =25 ? c ; avdd=lvdd=vdd33=3.0~3.6v( typ =3.3v, max =3.6v); tvdd=1.7~3.6v( typ =3.3v, max =3.6v); avss=dvss1=dvss2=dvss3=0v; fs=192khz; bick=64fs; master mode; sdout1~4/lrck1~3/bick1~3=output; c l =20pf) parameter symbol min. typ. max. unit power - up * 25 (pdn pin = h) = l
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 19 - 9. d igital filter characteristics adc block (ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33=3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v) 1. sharp roll - off filter (adsd bit = 0, adsl bit = 0) fs=48khz parameter symbol min. typ. max. unit sharp roll - off passband * 26 0db ~ - 0.06db pb 0 - 22.1 khz - 3.0db pb - 23.7 - khz stopband * 26 sb 27.8 - - khz stopband attenuation sa 85 .0 - - db group delay distortion : 0hz~20khz ? ? ?
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 20 - 2. slow roll - off filter (adsd bit = 0, adsl bit = 1) fs=48khz parameter symbol min. typ. max. unit slow roll - off passband * 26 0db ~ - 0.074db pb 0 - 12.5 khz - 3.0db pb - 19.2 - khz stopband * 26 sb 36.5 - - khz stopband attenuation sa 85 .0 - - db group delay distortion : 0hz~20khz ? ? ?
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 21 - 3. short delay sharp roll - off filter (adsd bit = 1, adsl bit = 0) fs=48khz parameter symbol min. typ. max. unit short delay sharp roll - off passband * 26 0db ~ - 0.06db pb 0 - 22.1 khz - 3.0db pb - 23.7 - khz stopband * 26 sb 27.8 - - khz stopband attenuation sa 85 .0 - - db group delay distortion : 0hz~20khz ? ? ?
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 22 - 4. short delay slow roll - off filter (adsd bit = 1, adsl bit = 1) fs=48khz parameter symbol min. typ. max. unit short delay slow roll - off passband * 26 0db ~ - 0.074db pb 0 - 12.5 khz - 3.0db pb - 19.2 - khz stopband * 26 sb 36.5 - - khz stopband attenuation sa 85 .0 - - db group delay distortion : 0hz~20khz ? ? ? a reference value of each gain amplitude is the maximum value of frequency response. * 27 . d elay time caused by the digital filter calculation. this time is measured from an analog sign al input until 24 - bit data of both channels are set into the output register. it includes group delay by hpf .
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 23 - dac block ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33=3.0~3.6v; avss=dvss1=dvss2=dvss3=0v) 1. sharp roll - off filter (dasd bit = 0, dasl bit = 0) fs= 48 khz parameter symbol min. typ. max. unit sharp roll - off passband * 28 ? ? ? ? ? ? ? ? ? pb = 0.4535 ? fs , sb = 0.546 ? fs * 29 . pas s - band gain amplitude of double over sampling filter at the first step of interpolator . * 30 . d elay time caused by the digital filter calculation. this time is measured from setting of the 16/20/24/32 - bit impulse data to the input registers to output of the analog peak signal. * 31 . the output level with a 1khz, 0db sine wave inp ut is defined as 0db. * 32 . band width of sto pband attenuation ranges from 0 hz to fs.
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 24 - 2. slow roll - off filter (dasd bit = 0, dasl bit = 1) fs= 48 khz parameter symbol min. typ. max. unit slow roll - off passband * 33 ? ? ? ? ? ? ? ? ? pb = 0.185 ? fs , sb = 0.888 ? fs
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 25 - 3. short delay sharp roll - off filter (dasd bit = 1, dasl bit = 0) fs= 48 khz parameter symbol min. typ. max. unit short delay sharp roll - off passband * 28 ? ? ? ? ? ? ? ? ?
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 26 - 4. short delay slow roll - off filter (dasd bit = 1, dasl bit = 1) fs= 48 khz parameter symbol min. typ. max. unit short delay slow roll - off passband * 34 ? ? ? ? ? ? ? ? ? pb = 0.252 ? fs , sb = 0.864 ? fs
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 27 - src block ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33=3.0~3.6v; avss=dvss1=dvss2=dvss3=0v ) 1. audio mode (srcfaud bit = 1, srcfec bit = 0) note * 35 . this val u e is src block only. it is the time from a rising edge of input lrck after data is input to a rising edge of output lrck just before the data is output when there is no phase difference between input and output lrck . parameter symbol min. typ. max. unit passband - 0.01db 0.980 fso/fsi 6.000 pb 0 - 0.4583fsi khz - 0.01db 0.900 fso/fsi < 0.990 pb 0 - 0.4167fsi khz - 0.01db 0.533 fso/fsi < 0.909 pb 0 - 0.2182fsi khz - 0.01db 0.490 fso/fsi < 0.539 pb 0 - 0.2177fsi khz - 0.01db 0.450 fso/fsi < 0.495 pb 0 - 0.1948fsi khz - 0.01db 0.225 fso/fsi < 0.455 pb 0 - 0.1312fsi khz - 0.50db 0.167 fso/fsi < 0.227 pb 0 - 0.0658fsi khz stopband 0.980 fso/fsi 6.000 sb 0.5417fsi - - khz 0.900 fso/fsi < 0.990 sb 0.5021fsi - - khz 0.533 fso/fsi < 0.909 sb 0.2974fsi - - khz 0.490 fso/fsi < 0.539 sb 0.2812fsi - - khz 0.450 fso/fsi < 0.495 sb 0.2604fsi - - khz 0.225 fso/fsi < 0.455 sb 0.1802fsi - - khz 0.167 fso/fsi < 0.227 sb 0.0970fsi - - khz passband ripple 0.225 fso/fsi 6.000 pr - - 0.01 db 0.167 fso/fsi < 0.227 pr - - 0.50 db stopband attenuation 0.450 fso/fsi 6.000 sa 95.2 - - db 0.167 fso/fsi < 0.455 sa 85.0 - - db group delay * 35 (ts=1/fs) gd - 6 7 ( 55 /fsi+ 12 /fso) - ts
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 28 - 2. voice mode (srcfaud bit = 0, srcfec bit = 0) 3. echo canceller mode (srcfec bit = 1) parameter symb ol min. typ. max. unit passband - 0.01db 0.980 passband - 0.01db 0.167
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 29 - 10. dc characteristics ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33=3.0~3.6v; avss=dvss1=dvss2=dvss3=0v) parameter symbol min. typ. max. unit high - level input voltage 1 * 36 vih1 75 %tvdd - - v low - level input voltage 1 * 36 vil1 - - 2 5 %tvdd v high - level input voltage 2 * 37 vih2 75 %vdd33 - - v low - level input voltage 2 * 37 vil2 - - 2 5 %vdd33 v scl, sda high - level input voltage vih3 70%tvdd - - v scl, sda low - level input voltage vil3 - - 30%tvdd v high - level output voltage iout= - 100 ? ? ? ? 2.0v (iout=3ma) vol3 - - 0.4 v tvdd < 2.0v (iout=3ma) vol3 - - 20%tvdd v fast mode plus tvdd 2.0v (iout=20ma) vol3 - - 0.4 v tvdd < 2.0v (iout=3ma) vol3 - - 20%tvdd v input leak current * 40 iin - - 10 ? ? ? ? ? l ) , the pull down resistors of lrck1, bick1, lrck2/jx1, bick2/jx2, lrck3 and bick3 pins is 50 k (typ. @3.3v) . * 42 . w hen the ak 7735a is powered up (pdn pin = h ) , the pull down resistors of lrck1, bick1, lrck2/jx1, bick2/jx2, lrck3 and bick3 pin s is 4 6 k (typ. @3.3v) . * 43 . leak current in case of inputting 3.3v when lvdd=tvdd=vdd33=3.3v .
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 30 - 11. switching characateristics system clock ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v; c l =20pf) parameter symbol min. typ. max. unit xti input timing a) xtal oscillator clko output timing output frequency fclko 2.048 - 24.576 mhz duty cycle dclko - 50 - % lrck/bick input timing (slave mode) lrck input timing frequency fs 8 - 192 khz bick input timing frequency * 44 fbclk 0.256 - 24.576 mhz pulse width low tbclkl 0.4 / fbclk - - ns pulse width high tbclkh 0.4 / fbclk - - ns lrck/bick output timing (pll master mode) lrck output timing frequency fs 8 - 192 khz pulse width high pcm mode except pcm mode tlrckh tlrckh - - 1/fbclk 50 - - ns % bick output timing frequency * 44 fbclk 0.256 - 24.576 mhz duty dbclk - 50 - % note * 44 . required to meet the following expression: fbc l k 2 x fs x ( input/output data length ) . power down ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v) parameter symbol min. typ. max. unit pdn pulse width * 45 trst 600 - - ns note * 45 . the pdn pin must be l when power up the ak 7735a . figure 3 . reset timing vil 1 trst pdn
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 31 - serial data interface (sdin1 ~ sdin4, sdout1 ~ sdout4) ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v; c l =20pf) parameter symbol min. typ. max. unit slave mode delay time from bick bick delay time from bick to serial data output master mode bick frequency fbclk - 32, 48, 64, 128, 256 - fs bick duty cycle - 50 - % delay time from bick when the bick polarity is inverted by setting bckpx bit = 1 . * 47 . it is measured from bick when the bick polarity is inverted by setting bckpx bit = 1 . * 48 . set sdophx bit to 1 and the data from sdoutx pin is output based on bick when bick speed is more than 12.288mhz such as when using tdm256 mode with 96khz sampling frequency or tdm128 mode with 192khz sampling frequency in slave mode. sdophx bit must be set to 0 in master mode.
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 32 - 1. slave mode figure 4 . serial interface input timing in slave mode figure 5 . serial interface output timing in slave mode (sdophx bit = 0 ) figure 6 . serial interface output timing in slave mode (sdophx bit = 1 ) tbsids tblrd tlrbd d vih 1/2 d vil 1/2 1~2 d tbsidh sdin 1 ~ 4 lrck 1~3 (i) bick 1~3 (i) vih 1/2 d vil 1/2 d vih 1/2 d vil 1/2 d vih 1/2 lrck 1~3 (i) bick 1~3 (i) vil 1/2 sdout 1~ 4 50% t vdd tbsod 1 d vih 1/2 vil 1/2 50% vdd33 tblrd tlrbd d tbsod1 d vih 1/2 lrck 1~3 (i) bick 1~3 (i) vil 1/2 sdout 1~ 4 50% t vdd tbsod 2 d vih 1/2 vil 1/2 50% vdd33 tblrd tlrbd d tbsod2 d
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 33 - 2. master mode figure 7 . serial interface input timing in master mode figure 8 . serial interface output timing in master mode (sdophx bit = 0) tbsids tmbl tmbl d lrck 1~3 (o) bick 1~3 (o) vih1/2 1/2 1/2 1 d vil 1/2 tbsidh sdin1~ 4 50%tvdd 50% vdd33 50%tvdd 50% vdd33 tbsod d lrck 1~3 (o) bi ck 1~3 (o) sdout 1~4 50%tvdd 50% vdd33 50%tvdd 50% vdd33 5 0%tvdd 50% vdd33 tbsod d
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 34 - spi interface ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v; c l =20pf) 1. spi low speed mode parameter symbol min. typ. max. unit p interface signal sclk frequency * 50 fsclk - - 3.0 mhz sclk low - level width tsclkl 160 - - ns sclk high - level width tsclkh 160 - - ns microcontroller ak 7735a csn high - level width twrqh 300 - - ns from csn to pdn trst 360 - - ns from pdn to csn tirrq 1 - - ms from csn to sclk twsc 300 - - ns from sclk to csn tscw 480 - - ns si latch setup time tsis 120 - - ns si latch hold time tsih 120 - - ns ak 7735a microcontroller delay time from sclk to so output tsos - - 120 ns so output hold time from sclk * 49 tsoh 120 - - ns 2. spi high speed mode parameter symbol min. typ. max. unit p interface signal sclk frequency * 50 fsclk - - 6 mhz sclk low - level width tsclkl 72 - - ns sclk high - level width tsclkh 72 - - ns microcontroller ak 7735a csn high - level width twrqh 150 - - ns from csn to pdn trst 180 - - ns from pdn to csn tirrq 1 - - ms from csn to sclk twsc 150 - - ns from sclk to csn tscw 240 - - ns si latch setup time tsis 60 - - ns si latch hold time tsih 60 - - ns ak 7735a microcontroller delay time from sclk to so output tsos - - 60 ns so output hold time from sclk * 49 tsoh 60 - - ns notes * 49 . except when writ ing the 24 th bit (8 bits command + 16 bits address) of the command code . this will be the 8th bit (8 bits command) with write preparation data read command ( 0x 24, 0x 25, 0x 26 and 0x 27) . * 50 . dummy command writing for switch ing to spi interface from i 2 c interface and control register access can always be made in spi high speed mode (max. 6mhz) . d sp ram area can be accessed in spi low speed mode (max. 3mhz) in clock reset state (ckresetn bit = 0 ) and can also be accessed in spi high speed mode (max. 6mhz) when pll is locked (ckresetn bit = 1 and pll is locked). i t is necessary to set dlrdy bit to 1 when accessing to the dsp ram area while pll is unlocked .
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 35 - figure 9 . spi interface timing 1 figure 10 . spi interface timing 2 (microcontroller ak 7735a ) figure 11 . spi interface timing 3 ( ak 7735a microcontroller) tsclkh tsclkl 1/fsclk 1/fsclk sclk vih 1 vil 1 vih 1 vil 1 vih 1 vil 1 trst pd n csn tirrq twrqh tsis tsih tscw tscw twsc tscw cs n si vih 1 vil 1 vih 1 twsc sclk vil 1 vih 1 vil 1 tsos tsoh sclk vil 1 vih 1 so 50%tvdd
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 36 - i 2 c interface ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v) 1. i 2 c: fast mode parameter symbol min. typ. max. unit i 2 c timing scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - ? s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - ? s clock low time tlow 1.3 - - ? s clock high time thigh 0.6 - - ? s setup time for repeated start condition tsu:sta 0.6 - - ? s sda hold time from scl falling thd:dat 0 - - ? s sda setup time from scl rising tsu:dat 0.1 - - ? s rise time of both sda and scl lines tr - - 0.3 ? s fall time of both sda and scl lines tf - - 0.3 ? s setup time for stop condition tsu:sto 0.6 - - ? s pulse width of spike noise suppressed by input filter tsp 0 - 50 ns capacitive load on bus cb - - 400 pf 2. i 2 c: fast mode plus parameter symbol min. typ. max. unit i 2 c timing scl clock frequency fscl - - 1 mhz bus free time between transmissions tbuf 0.5 - - ? s start condition hold time (prior to first clock pulse) thd:sta 0.26 - - ? s clock low time tlow 0.5 - - ? s clock high time thigh 0.26 - - ? s setup time for repeated start condition tsu:sta 0.26 - - ? s sda hold time from scl falling thd:dat 0 - - ? s sda setup time from scl rising tsu:dat 0.05 - - ? s rise time of both sda and scl lines tr - - 0.12 ? s fall time of both sda and scl lines tf - - 0.12 ? s setup time for stop condition tsu:sto 0.26 - - ? s pulse width of spike noise suppressed by input filter tsp 0 - 50 ns capacitive load on bus cb - - 550 pf figure 12 . i 2 c interface timing thigh scl sda vih 3 tlow tbuf thd:sta t r tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil 3 vih 3 vil 3 tsp
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 37 - 12. recommended external circuits connection diagram 1. i 2 c interface figure 13 . i 2 c interface connection example sdout1/rdy 20 28 s da scl 26 25 up 45 pdn reset control ak77 35 a vrefh audio i/f clock csn 24 h or l & 23 sto/ rdy/ sdout 2 sdin 1 17 42 analog +3.3 v avdd 10 ? 0.1 ? vcom 44 2.2 ? dvs s 1/dvss2 /dvss3 10, 22 , 30 21 digital io 1.8 3.3 v t vdd 10 ? 0.1 ? 11 digital io 3.3 v vdd33 10 ? 0.1 ? 31 digital core 3.3 v lvdd 10 ? 0.1 ? vrefl avss avdrv 2.2 ? 2 aout1r 47 aout1l 48 aout2l aout2r 1 i2cfil 27 h or l sdin 2 /jx0 lrck 1 18 bick 1 19 lrck 2 /jx1 15 bick 2 /jx2 16 sdout 3/clko/gpo1 7 sdin 3 /jx3 sdin 4 9 sdout 4/ gpo 2 5 lrck 3 4 bick 3 6 audio i/f clock & testi 3 l 8 29 46 43 35 ain2lp/ain3l 34 ain2ln/ain4l 33 ain2rp/ain3r 32 ain2r n /ain4r 39 ain 1l /inp1 38 inn1 37 ain 1r / inp2 36 inn2 41 mpwr mpref 40 1 ? 4.7 k 4.7 k 4.7 k 4.7 k 10 ? 0.1 ? 1 ? 1 ? 1 ? 1 ? 100n 100n 100n 100n xto xti rd 12 13 14 1 ? 1 ? 1 ? 1 ?
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 38 - 2. spi interface figure 14 . spi interface connection e x ample sdout1/rdy 20 28 so sclk 26 25 up 45 pdn reset control ak77 35 a vrefh audio i/f clock csn 24 & 23 sto/ rdy/ sdout 2 sdin 1 17 42 analog +3.3 v avdd 10 ? 0.1 ? vcom 44 2.2 ? dvss 1/dvss2 /dvs s3 10, 22 , 30 21 digital io 1.8 3.3 v t vdd 10 ? 0.1 ? 11 digital io 3.3 v vdd33 10 ? 0.1 ? 31 digital core 3.3 v lvdd 10 ? 0.1 ? vrefl avss avdrv 2.2 ? 2 aout1r 47 aout1l 48 aout2l aout2r 1 si 27 sdin 2 /jx0 lrck 1 18 bick 1 19 lrck 2 /jx1 15 bick 2 /jx2 1 6 sdout 3/clko/gpo1 7 sdin 3 /jx3 sdin 4 9 sdout 4/ gpo 2 5 lrck 3 4 bick 3 6 audio i/f clock & testi 3 l 8 29 46 43 35 ain2lp/ain3l 34 ain2ln/ain4l 33 ain2rp/ain3r 32 ain2r n /ain4r 39 ain 1l /inp1 38 inn1 37 ain 1r /inp2 36 inn2 41 mpwr mpref 40 1 ? 4.7 k 4.7 k 4.7 k 4.7 k 10 ? 0.1 ? 1 ? 1 ? 1 ? 1 ? 100n 100n 100n 100n xto xti rd 12 13 14 1 ? 1 ? 1 ? 1 ?
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 39 - peripheral circuit 1. ground avss, dvss1, dvss2 and dvss3 should be connected to the same ground. decoupling capacitors, pa rticularly ceramic capacitors of small capacity, should be placed at positions as close as possible to the ak 7735a . 2. reference voltage vcom is a common voltage of this chip and the vcom pin outputs avdd/2. a 2.2f ceramic capacitor should be connecte d between the vcom pin and a vss. do not connect the vcom pin to any external devices. digital signal lines, especially clock signal line should be kept away as far as possible from this pin in order to avo id unwanted coupling into the ak 7735a . 3. analog input the analog input signal is input to the analog modulator of the ak 7735a . the maximum input voltage at differential input pins is 2. 30vpp (typ.) or 2. 83vpp (typ.) . the maximum input voltage at single - ended input pins is 2. 30vpp (typ.) or 2. 83vpp ( typ.) . the output code format is 2's complements. the internal hpf removes the dc offset . after power - down is released, the internal operating point level avdd/2 occurs on analog input pins of the ak 7735a . concerning the internal operating point formation circuit, each input pin has impedance of 2 5 k ? ( t yp . ). the pins that are connected to ac coupling capacitors require start - up time (time constant). the ak 7735a samples the analog inputs at 6.144 mhz when fs=48khz , 96khz or 192khz . the ak 7735a includes an anti - aliasing filter (rc filter) , and n o external low - pass filter is necessary in front of the adc. however, an external low - pass filter should be connected before the adc for the signal which has large out - of - band noise such as d/a converted signals. the analog power supply to the ak 7735a is +3.3v (t yp .) . voltage of avdd + 0.3v or larger , voltage of a vss - 0.3v or smaller , and current of 10ma or larger must not be applied to analog input pins. excessive current will damage the internal protec tion circuit and will cause latch - up, damaging the ic. accordingly, if the e xternal analog circuit voltage is 15v, the analog input pins must be protected from signals which are equal or larger than absolute maximum rating s . 4. analog output the analog output is single - ended and the output signal range is typically 0. 857 x avdd vpp centered on v com . the digital input data format is two s compliment. positive full - scale output corre sponds to 0x 7ffff ff f (@ 32 bit) inpu t code, negative full scale is 0x 80 00 0000 (@ 32 bit) and vcom voltage ideally is 0x 000 00 000 (@ 32 bit) . the out - of - band noise (shaping noise) generated by the internal delta - sigma modulator is attenuated by an integrated switched capacitor filter (scf) and a continuous time filter (ctf).
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 40 - 5 . crystal oscillator the resistor and capacitor values for the oscillator rc circuit are shown blow. oscillator r1 ( max ) ( * 51 ) c0 ( max ) ( * 51 ) xti, xto pin capacity 12.288mhz 120 80 xto xti cl cl c1 c0 r1 l1
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 41 - 13. package outline dimensions material and lead finis h package: epoxy , halogen (br and ci) free lead frame: copper lead - finish: soldering (pb free) plate
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 42 - marking 1) pin #1 indication 2) date code: xxxxxxx (7 digits) 3) marking code: ak 7735a vq 4) asahi kasei logo ak77 35 a vq xxxxxxx 1 akm
[ ak 7735a ] 018002104 - e - 00 - pb 201 8/03 - 43 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipu lated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application ex amples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may c ause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, train s, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use produ ct for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human li fe, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, f or the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this docu ment, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manu facture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in co mpliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with a pplicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

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